Cerebras did what the industry calls impossible: turned an entire 46,225mm² wafer into one chip. Defects on silicon that…
SemiAnalysis Twitter · SemiAnalysis (@SemiAnalysis_) · 2026-06-02
SemiAnalysis details how Cerebras achieved wafer-scale integration of a single 46,225mm² chip by engineering defect redundancy and custom per-batch routing masks that route around faulty cores, yielding near 100% usable wafers despite inevitable silicon defects at that scale.
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Topics: cerebraswafer-scale-aichip-defect-managementsemiconductor-manufacturing
Claims
- Cerebras turned an entire 46,225mm² wafer into a single chip, which the industry considered impossible.
- Silicon defects are inevitable at wafer scale and Cerebras designed around them rather than attempting to eliminate them.
- Cerebras builds in redundancy and creates custom per-batch masks to route around every defective core.
- This approach achieves near 100% usable wafer yield despite the large defect probability.
Key quotes
Cerebras did what the industry calls impossible: turned an entire 46,225mm² wafer into one chip.
Defects on silicon that big are inevitable, so they built in redundancy and custom per-batch masks that route around every bad core, landing near 100% usable wafers.