IBM claims world’s first sub-1 nanometer chip technology
Ars Technica AI · Jeremy Hsu · 2026-06-25
IBM announces a 'nanostack' chip architecture that delivers sub-1-nanometer equivalent performance by integrating nearly 100 billion transistors on a fingernail-sized chip, roughly doubling its previous transistor density for AI data center applications.
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Extraction
Topics: semiconductor-technologychip-architectureai-hardwareibm-research
Claims
- IBM's new nanostack architecture integrates nearly 100 billion transistors on a chip the size of a human fingernail, nearly twice the density of its previous generation.
- The 'sub-1 nanometer' claim refers to performance equivalence rather than literal physical feature size, since chips with physical features below 1 nanometer are impractical to manufacture reliably.
- The nanostack architecture improves both compute performance and energy efficiency specifically for AI data center workloads.
- IBM characterizes this advance as a meaningful leap forward, not an incremental step, in chip computing power.
Key quotes
It's not just an incremental step, it's a meaningful leap forward — pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy.
IBM is basically claiming that its new 'nanostack' architecture can deliver the computing performance improvements that would be expected if a theoretical chip could be built with physical features smaller than 1 nanometer.
It is impractical to build reliably functional chips with transistors and other features smaller than 1 nanometer due to various physical limitations.