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A cluster of efficiency results from June 9–17, 2026 challenges the assumption that AI capability and inference cost scale with model size. The main findings: MiniMax Sparse Attention (MSA) cuts attention compute 28.4x at 1-million-token contexts [3]; removing KV projection matrices halves cache size at 3.1% perplexity cost [5]; a 4B-parameter model outperforms a 671B model on formal theorem proving [6]; and Tensordyne announced its Napier processor, claiming 17x tokens-per-watt and 13x throughput over NVIDIA Blackwell using logarithmic arithmetic [8]. The Tensordyne claim has since attracted coverage from Forbes, IEEE Spectrum, NextPlatform, and ServeTheHome, with IEEE Spectrum describing the figures as 'bold' [12][11][10].

Independent efficiency gains are appearing across hardware, model architecture, memory management, and agent systems simultaneously. If the key claims hold under independent testing, the combined effect on inference cost would be large without requiring larger models or more compute.

A cluster of efficiency results published between June 9 and 17, 2026 puts pressure on the assumption that AI capability and inference cost scale primarily with parameter count. The findings come from different parts of the stack — attention computation, KV memory design, training data geometry, hardware arithmetic, and agent context management — and are not products of a single coordinated research program.

The most extensively covered result comes from MiniMax, which released its M3 model alongside a paper describing MiniMax Sparse Attention (MSA) [1][2]. Full attention computes relevance between every pair of tokens in a sequence, making computation grow quadratically with context length. MSA selectively attends to a subset of tokens, cutting attention compute 28.4x at 1-million-token contexts and delivering 14.2x faster prefill and 7.6x faster decoding on H800 GPUs while mostly matching full-attention benchmark performance [3]. NVIDIA published a technical blog covering deployment of M3 on its accelerated infrastructure [4], adding third-party institutional acknowledgment. Three other software-layer results extend the case: removing KV projection matrices halves cache size at a 3.1% perplexity penalty [5]; Pythagoras-Prover (4B parameters) outperforms DeepSeek-Prover-V2-671B on the MiniF2F Pass@32 benchmark, attributed to improved training data geometry [6]; and TokenPilot achieves 61–87% agent cost reductions by replacing prompt truncation with ingestion-aware compaction [7].

The hardware angle centers on Tensordyne's Napier processor, announced around June 15–16 and built around logarithmic arithmetic implemented directly in silicon rather than as a software approximation [8]. Tensordyne claims 17x higher tokens per watt and 13x higher throughput than NVIDIA Blackwell [9]. The announcement drew coverage from Forbes, which framed it around AI power consumption [10], NextPlatform, which examined the mechanism of converting matrix math to logarithms [11], ServeTheHome [8], and IEEE Spectrum, which described the efficiency figures as 'bold' [12] — the clearest signal of editorial skepticism so far. No independent replication of Tensordyne's claimed figures exists, and the company's comparisons are drawn from its own materials [13][14][15].