So why EMIB?
SemiAnalysis Twitter · SemiAnalysis (@SemiAnalysis_) · 2026-07-01
SemiAnalysis explains that Intel's EMIB packaging surpasses TSMC's CoWoS in scalability and cost by embedding small silicon bridges in organic substrate, eliminating the reticle size limit and interposer waste that constrain CoWoS at large die counts.
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Extraction
Topics: semiconductor-packagingintel-emibtsmc-cowoschiplet-architecture
Claims
- EMIB is not subject to the lithography reticle size limit that caps CoWoS silicon interposers, making it inherently more scalable.
- EMIB packaging is meaningfully cheaper than CoWoS because it eliminates the costly monolithic silicon interposer.
- Small EMIB bridges tile densely on round wafers with minimal edge waste, while large CoWoS interposers suffer poor yield at the wafer edge.
- EMIB gives AI accelerator buyers a second advanced packaging source outside of TSMC, reducing supply concentration risk.
Key quotes
EMIB isn't bound by the interposer reticle limit... it's a much more scalable technology.
EMIB packaging is meaningfully cheaper, since it drops the costly interposer entirely.
It also gives buyers a second source outside TSMC.