Google Humufish TPU Abandons TSMC CoWoS for Intel EMIB-T Advanced Packaging

Google's next-generation TPU, codenamed Humufish (TPU v8e), is reported to use Intel's EMIB-T advanced packaging rather than TSMC's CoWoS — the standard for virtually every current AI training accelerator.[1] Google has reportedly booked Intel for over 3 million Humufish units targeting 2028 production.[4][3] TSMC's CEO has publicly warned that CoWoS supply will remain tight for years,[9] providing the commercial backdrop for Google's move. The central uncertainty is whether Intel can manufacture EMIB-T — which adds integrated power delivery to the standard EMIB bridge and has not yet shipped in volume — at the yield and throughput the order requires.[7][8]

CoWoS is the uncontested packaging default for AI accelerators; a major Google TPU generation moving off it would be the first significant defection from TSMC's packaging dominance. If Intel's EMIB-T ramp succeeds, it validates a second credible source for advanced AI accelerator packaging and reduces the industry's concentration risk around TSMC. If the ramp fails, Google faces a production gap with no ready alternative.[7]

Google's next TPU generation, codenamed Humufish (TPU v8e), is being designed around Intel's EMIB-T packaging rather than TSMC's CoWoS, according to SemiAnalysis and corroborated by multiple trade outlets.[1][2] The decision is significant because CoWoS is the packaging baseline for virtually every high-end AI training accelerator currently in production, making Humufish a notable departure from the industry default.[1] Google has reportedly placed an order with Intel for over 3 million units targeting 2028 production.[3][4][5]

EMIB (Embedded Multi-die Interconnect Bridge) differs structurally from CoWoS. Where CoWoS places all dies on a single large silicon or redistribution-layer interposer, EMIB embeds small silicon bridges directly in the organic substrate only at die-to-die connection points.[1] SemiAnalysis identifies three structural advantages: EMIB is not constrained by the lithography reticle size limit that caps CoWoS interposers, making it more scalable for future, larger designs; it eliminates the costly monolithic interposer, reducing package cost; and small bridges tile efficiently on wafers with less edge waste.[6] A further advantage is supply diversification — Intel packaging gives hyperscalers a second source outside TSMC for advanced 2.5D integration.[6]

The risk centers on EMIB-T specifically. Standard EMIB has shipped in production volumes for years and its manufacturability is established. EMIB-T adds integrated power delivery through the bridge itself, which is technically novel and has not been produced at scale.[7] SemiAnalysis judges that a power-delivering bridge is harder to manufacture than a standard bridge, and that if Intel's ramp slips, Google's only fallback is CoWoS — the same capacity-constrained technology EMIB-T was chosen to replace.[7] Ming-Chi Kuo has separately reported Intel's current EMIB yield at roughly 90%, which he characterizes as insufficient for volume production requirements.[8]

TSMC CoWoS supply pressure provides the broader context. TSMC's CEO has said the supply gap will persist for years, with CoWoS revenue still up 30% year-over-year in May 2026.[9] AMD and NVIDIA are reported to be competing for 2027 Taiwan packaging capacity.[10] A New York Times report from late June 2026 framed advanced chip packaging as having become a choke point for the AI industry.[11] SK Hynix is also reported to be testing Intel's EMIB packaging for HBM integration,[4] suggesting Google may not be the only player routing demand toward Intel packaging.