EMIB-T Roadmap, Custom HBM,
SemiAnalysis Twitter · SemiAnalysis (@SemiAnalysis_) · 2026-07-02
SemiAnalysis publishes a technical roundup of ECTC 2026 disclosures covering Intel's EMIB-T advanced packaging roadmap, Marvell's custom HBM interface work, microfluidic cooling from TSMC and Microsoft, and photonic interconnects from Marvell and Lightmatter, all targeting next-generation AI accelerator packages.
Appears in
Extraction
Topics: semiconductor-packagingemib-thbm4microfluidic-coolingphotonic-interconnectsai-hardware
Claims
- Advanced packaging has become the primary AI hardware scaling vector as transistor density scaling has slowed.
- Intel validated EMIB-T at a 36/35 µm bump pitch on 2× reticle-sized packages and is expanding to 4.5× reticle packages, with 25 µm pitch testing underway.
- Intel demonstrated a 240 mm × 240 mm quarter-panel EMIB-T test vehicle, though severe warpage was observed at that scale.
- EMIB-T is the most credible alternative to TSMC's CoWoS platform for large-package AI accelerators, and is expected to be used in Google's TPU v9.
- HBM4E doubles I/O count while increasing speed, straining conventional package and cooling architectures.
Key quotes
As transistor density scaling has slowed, advanced packaging has become the primary scaling vector.
EMIB-T is expected to be used in Google's TPU v9, and why it is the most credible alternative to TSMC's CoWoS platform for large-package AI accelerators.
Below 25 µm, the solder volume in each bump becomes very small. Shorts, opens, and assembly-driven yield loss become much more likely.