Google Reveals TPUv8t and Virgo 134K-Chip Scale-Out Interconnect

Google announced the TPUv8t, a training-focused TPU, alongside Virgo, a new scale-out interconnect capable of linking up to 134,400 chips with 47 Pbps of non-blocking bi-sectional bandwidth.[1] The TPUv8t delivers 4x the bandwidth per accelerator and 40% lower latency versus the previous generation.[2] SemiAnalysis published detailed topology specs covering both the intra-pod 3D Torus ICI and the flat two-layer inter-pod Virgo network,[3][2] and simultaneously launched a paid AI Networking Model covering hyperscaler switch and transceiver configurations at scale.[4]

Virgo's scale — 134,400 chips, 47 Pbps bisectional bandwidth — represents a substantial expansion in the chip count Google can pool for a single training run. The flat two-layer inter-pod topology, rather than a deeper hierarchy, is a design choice with direct implications for cost, latency, and how competitors structure their own scale-out networks.

Google introduced the TPUv8t as a training-focused accelerator and paired it with Virgo, a new scale-out interconnect architecture. Virgo can link up to 134,400 chips simultaneously, providing up to 47 Pbps of non-blocking bi-sectional bandwidth — Google frames this as 4x the bandwidth per accelerator and 40% lower latency relative to the prior TPU generation.[1][2]

The physical architecture, as detailed by SemiAnalysis, separates intra-pod and inter-pod networking. Within each pod, 9,600 TPUs communicate over a 3D Torus ICI; 14 such pods connect over Virgo's inter-pod fabric. That fabric uses a flat two-layer topology. At the switch level, L1 switches connect to one another in full mesh via 800G 2xFR4 OSFPs operating in 8x100G breakout mode; L2 switches use 400G FR4 QSFPs in 4x100G breakout mode. To maintain a non-blocking topology across both layers, Google doubles certain links between L1 and L2.[3][2]

SemiAnalysis published the Virgo breakdown as part of a four-post thread on June 3, 2026, and used the moment to announce a new AI Networking Model — a paid analytical product covering 80+ configuration panels that detail switch, transceiver, cable, AEC, and DAC counts, pricing, and power per hyperscaler across H100-to-GB300 NVL configurations, alongside optical market forecasts across 200G through 1.6T segments through 2026.[4] Other analysts, including GlobalSemiResearch and FundaAI, published concurrent deep dives[5][6], and Google's own Cloud Blog posted a technical breakdown.[7] The specific claims from those sources are not yet fully extracted in this synthesis pass.

The broader item pool attached to this thread contains substantial noise — off-topic financial commentary, AMD market cap posts, and Computex Keynote read-throughs — that was captured by the wide-net reactive queries but carries no content relevant to the TPUv8t or Virgo.