Version 1

The primary constraint on frontier AI hardware has migrated from GPU availability to High Bandwidth Memory (HBM) wafer supply, with CoWoS packaging no longer the binding bottleneck [1][2].

SemiAnalysis research shows AI consuming roughly 60% of TSMC's N3-family wafers in 2026, rising to approximately 86% by 2027 — a regime change in leading-edge chip market dynamics [3].

At those concentration levels, SemiAnalysis argues the supply curve for frontier AI accelerators is effectively a policy decision inside TSMC, Apple, and Samsung, not a conventional market-driven capacity question [6].

Most consensus accelerator demand models, SemiAnalysis contends, have not caught up to where N3 demand is actually heading [7].

If SemiAnalysis is correct, the standard investment and planning framework for AI hardware — model capacity expansion as a market signal — is broken. When two or three companies' internal allocation choices determine supply, the shortage becomes structural and geopolitically exposed rather than a problem engineering investment alone can solve. The shift of scarcity from GPUs to HBM also reshuffles which companies sit at the critical bottleneck.

For most of 2024 and 2025, the defining constraint on AI infrastructure was Nvidia GPU availability. That bottleneck then migrated to CoWoS advanced packaging — the substrate that bonds GPU dies to HBM memory stacks. According to SemiAnalysis's research published as 'The Great AI Silicon Shortage,' CoWoS supply has now substantially eased, but a new binding constraint has taken its place: the wafer supply for High Bandwidth Memory itself [1]. HBM demand from AI accelerator production is outrunning the capacity of memory fabs to supply wafers, and the competition for that capacity includes smartphone manufacturers, creating real allocation tradeoffs [1][2].

The N3 wafer picture is equally striking. SemiAnalysis estimates that AI applications will absorb roughly 60% of TSMC's entire N3-family wafer output in 2026, with that share projected to climb to approximately 86% in 2027 [3]. The firm frames 2027 as a structural inflection point: once AI is consuming nearly all of a leading-edge node, the elasticity that historically came from reallocating smartphone wafers becomes a much larger lever than it was when AI was a minority customer [3]. TSMC itself has publicly affirmed strong AI demand through 2027 and 2028 [4], and TrendForce reported in April 2026 that TSMC's 3nm monthly capacity may hit 180,000 wafers — up more than 40% year-over-year — driven by AI demand [5].

SemiAnalysis draws a structural conclusion from these numbers: at this concentration, the supply curve for frontier AI accelerators is no longer a market phenomenon. It is, in effect, a policy decision made inside TSMC, Apple, and Samsung — the three companies whose internal allocation choices determine how much AI silicon reaches customers [6]. Traditional supply-demand models, the firm argues, have not adapted to this reality, and most consensus accelerator forecasts materially underestimate where N3 demand is heading [7]. The broader implication is that analysis of AI hardware availability needs to shift from tracking capacity investment to tracking the internal strategic choices of a handful of fabs and their largest customers.

On the competitive periphery, Samsung is emerging as an overflow option as TSMC's capacity falls short for some customers [8][9], and the Asian AI chip race between TSMC, Samsung, and nascent Chinese semiconductor players continues to intensify [10]. But the fundamental picture SemiAnalysis paints is one of extreme concentration: a market where the scarcest resource is controlled by very few decision-makers, and where shortages in HBM and leading-edge wafers are not incidental frictions but structural features of the current AI infrastructure build-out.