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Google's next-generation TPU, codenamed Humufish, is designed to use Intel's EMIB-T advanced packaging rather than TSMC's CoWoS — the current industry standard for AI training accelerators.[1] Google has reportedly booked Intel for over 3 million units targeting 2028 production.[2][3] SemiAnalysis's follow-up analysis drawing on ECTC 2026 conference disclosures confirms Intel has validated EMIB-T at 36/35 µm bump pitch on 2× reticle-sized packages and is expanding toward 4.5× reticle, but observed severe warpage on a 240 mm × 240 mm quarter-panel test vehicle.[6] The central execution question is whether Intel can resolve warpage, push bump pitch below 25 µm without yield degradation, and reach volume production by 2028.[6][7]

CoWoS is the uncontested packaging default for AI accelerators; a major Google TPU generation moving off it would be the first significant defection from TSMC's packaging dominance. If Intel's EMIB-T ramp succeeds, it validates a second credible source for advanced AI accelerator packaging and reduces the industry's concentration risk around TSMC — which itself acknowledges CoWoS supply will stay tight for years.[11]

Google's next-generation TPU, codenamed Humufish, is being built around Intel's EMIB-T packaging technology rather than TSMC's CoWoS — the baseline for virtually every current high-end AI training accelerator.[1] The decision, reported by SemiAnalysis and corroborated across multiple trade outlets, involves a reported order of over 3 million units targeting 2028 production.[2][3][4] EMIB (Embedded Multi-die Interconnect Bridge) differs structurally from CoWoS: it uses small silicon bridges embedded in the organic substrate only at die-to-die connection points, avoiding the costly monolithic interposer and the reticle-size constraints that limit CoWoS scalability.[1][5] EMIB-T adds integrated power delivery through the bridge itself — technically novel and not yet in volume production.

SemiAnalysis has published additional technical grounding from ECTC 2026 conference disclosures. Intel has validated EMIB-T at 36/35 µm bump pitch on 2× reticle-sized packages and is expanding toward 4.5× reticle packages, with 25 µm pitch testing underway.[6] However, Intel demonstrated a 240 mm × 240 mm quarter-panel EMIB-T test vehicle at which severe warpage was observed — a mechanical reliability concern at the package dimensions relevant for large AI accelerators.[6] SemiAnalysis also flags that below 25 µm bump pitch, solder volume per bump becomes small enough that shorts, opens, and assembly-driven yield loss become significantly more likely.[6] The same analysis characterizes advanced packaging as the primary AI hardware scaling vector as transistor density scaling has slowed, and describes EMIB-T as the most credible alternative to TSMC's CoWoS for large-package AI accelerators.[6]

The risk picture has competing readings. SemiAnalysis presents EMIB-T as technically superior to CoWoS on scalability, cost, wafer economics, and supply diversification, while treating Intel's execution on warpage and yield as the open variable.[7][6] Ming-Chi Kuo has separately reported Intel's current EMIB yield at roughly 90%, which he characterizes as below volume-production requirements — a more pessimistic near-term read.[8] Taiwan's CommonWealth Magazine questions whether Google's commitment is final and could revert to TSMC if Intel misses targets.[9] Meanwhile, AMD and NVIDIA are competing for 2027 TSMC CoWoS capacity[10] and TSMC's CEO has said supply tightness will persist for years[11] — the capacity pressure that made Intel packaging attractive in the first place.

One naming detail is unresolved: SemiAnalysis's ECTC-based analysis refers to the target chip as 'TPU v9,' while its own earlier reporting and other outlets had consistently called the same chip 'TPU v8e (Humufish).'[6][1] Whether this reflects a product numbering revision or a reference to a separate generation has not been publicly clarified.