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Google Humufish TPU Abandons TSMC CoWoS for Intel EMIB-T Advanced Packaging · history

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2026-07-04 02:25 UTC · 97 items

What

Google's next-generation TPU, codenamed Humufish, is designed to use Intel's EMIB-T packaging rather than TSMC's CoWoS, with a reported order of over 3 million units targeting 2028 production.[2][3] MediaTek is reportedly exploring a dual Intel EMIB / TSMC CoWoS packaging strategy for its AI ASIC designs,[11] suggesting broader industry interest beyond Google. Intel has validated EMIB-T at 36/35 µm bump pitch on 2× reticle packages and is expanding toward 4.5× reticle, but severe warpage on a 240 mm × 240 mm test vehicle remains the central unresolved manufacturing risk.[5]

Why it matters

CoWoS has been the uncontested packaging standard for AI accelerators; a major Google TPU generation moving to Intel EMIB-T would be the first significant defection from TSMC's packaging dominance. MediaTek's reported dual-source approach, if confirmed, would mark a second major customer testing EMIB in production AI designs — moving it from a Google-specific experiment toward a genuine second-source market for advanced AI packaging.

Open questions

  • Can Intel resolve warpage at 240 mm × 240 mm scale and ramp EMIB-T to volume production by 2028?[5]

  • Will Intel's ability to push bump pitch below 25 µm — where yield loss from shorts and opens becomes significantly more likely — determine whether EMIB-T can match CoWoS density at scale?[5]

  • SemiAnalysis refers to the target chip as 'TPU v9' while earlier reports called it 'TPU v8e (Humufish)'; is this a naming update or a reference to a different product generation?[5][1]

  • Does MediaTek's reported dual Intel EMIB / TSMC CoWoS strategy represent genuine confidence in EMIB at production scale, or a hedging posture while Intel's yield matures?[11]

Narrative

Google's next-generation TPU, codenamed Humufish, is being built around Intel's EMIB-T packaging technology rather than TSMC's CoWoS — the baseline for virtually every current high-end AI training accelerator.[1] The decision, reported by SemiAnalysis and corroborated across multiple trade outlets, involves a reported order of over 3 million units targeting 2028 production.[2][3] Intel's role is packaging only — EMIB-T handles the die-to-die interconnect — not chip fabrication. EMIB (Embedded Multi-die Interconnect Bridge) differs from CoWoS by using small silicon bridges embedded in the organic substrate only at die-to-die connection points, avoiding the monolithic interposer and reticle-size constraints that limit CoWoS scalability.[1][4] EMIB-T adds integrated power delivery through the bridge itself, a feature not yet in volume production.

SemiAnalysis, drawing on ECTC 2026 conference disclosures, has published detailed technical grounding: Intel has validated EMIB-T at 36/35 µm bump pitch on 2× reticle-sized packages and is expanding toward 4.5× reticle, with 25 µm pitch testing underway.[5] A 240 mm × 240 mm quarter-panel EMIB-T test vehicle demonstrated severe warpage — a mechanical reliability concern at the package dimensions relevant for large AI accelerators.[5] SemiAnalysis also flags that below 25 µm bump pitch, solder volume per bump becomes small enough that shorts, opens, and assembly-driven yield loss become significantly more likely.[5] The same analysis describes EMIB-T as the most credible alternative to TSMC's CoWoS for large-package AI accelerators, with advanced packaging now the primary AI hardware scaling vector as transistor density scaling has slowed.

The risk picture has competing readings. SemiAnalysis presents EMIB-T as technically superior to CoWoS on scalability, cost, and supply diversification, treating Intel's execution on warpage and yield as the open variable.[6][5] Ming-Chi Kuo has reported Intel's current EMIB yield at roughly 90%, which he characterizes as below volume-production requirements — a more pessimistic near-term read.[7] Taiwan's CommonWealth Magazine questions whether Google's commitment is final and could revert to TSMC if Intel misses targets.[8] AMD and NVIDIA are simultaneously competing for 2027 TSMC CoWoS capacity,[9] and TSMC's CEO has said supply tightness will persist for years[10] — the capacity pressure that made Intel packaging attractive in the first place.

MediaTek is reportedly exploring a dual packaging strategy that uses both Intel EMIB and TSMC CoWoS for its AI ASIC designs,[11] which would make it a second significant customer testing EMIB in production AI packaging. WCCFTech has framed Intel's EMIB effort as the US industry's structural response to concentration in TSMC's CoWoS packaging supply,[12] adding a supply chain sovereignty dimension to what has primarily been covered as a technical and commercial story.

Timeline

  • 2026-05: Tom's Hardware reports Intel's EMIB-T packaging technology is on track for fab rollout in 2026, positioned for advanced AI accelerator designs. [19]
  • 2026-05-06: 247 Wall St reports AI chip packaging constraints are creating a commercial opening for Intel's EMIB technology. [16]
  • 2026-05-12: TrendForce reports MediaTek is adopting a dual packaging strategy using both Intel EMIB and TSMC CoWoS for its AI ASIC push. [11]
  • 2026-06: Ming-Chi Kuo reports Google's TPU v8e (Humufish) is designed for Intel EMIB-T packaging; notes current EMIB yield at ~90%, below volume-production requirements. [7][13]
  • 2026-06: Multiple outlets report Google has booked Intel for over 3 million Humufish TPU packages targeting 2028 production; SK Hynix also reported testing Intel EMIB for HBM integration. [2][3][14][15]
  • 2026-06: WCCFTech reports Intel's EMIB-T supply chain draws in two additional Taiwanese suppliers as part of the Google TPU buildout. [20]
  • 2026-06-26: New York Times publishes piece on advanced chip packaging becoming a supply choke point for AI. [17]
  • 2026-06-28: TSMC reports May revenue +30% YoY driven by CoWoS demand; CEO warns supply tightness will persist for years. [10]
  • 2026-06-30: AMD and NVIDIA reported competing aggressively for 2027 Taiwan packaging capacity. [9]
  • 2026-06-30: Glass substrate technology identified as a potential longer-term alternative to silicon interposers for AI chip packaging. [21]
  • 2026-07-01: SemiAnalysis publishes detailed analysis confirming Humufish will use EMIB-T, explaining technical advantages over CoWoS and flagging EMIB-T manufacturing maturity as the key execution risk. [6][4][1]
  • 2026-07-02: SemiAnalysis publishes ECTC 2026-based analysis: EMIB-T validated at 36/35 µm bump pitch on 2× reticle packages, expansion to 4.5× underway, but severe warpage observed on 240 mm × 240 mm test vehicle; refers to target as 'TPU v9.' [5]
  • 2026-07-03: WCCFTech frames Intel EMIB as the US industry's structural response to TSMC's CoWoS packaging concentration. [12]

Perspectives

SemiAnalysis

EMIB-T is technically superior to CoWoS on scalability, cost, and supply diversification; Intel has validated it at 36/35 µm pitch on 2× reticle packages and is expanding to 4.5×, but warpage at 240 mm × 240 mm scale and sub-25 µm yield risk are the unresolved manufacturing questions.

Evolution: Consistent on technical superiority argument; ECTC 2026 analysis added concrete validation data and surfaced warpage and fine-pitch yield as specific risk vectors.

[6][4][1][5]

Ming-Chi Kuo

Intel's current EMIB yield (~90%) is below volume-production requirements; Google's adoption is a supply-chain gamble contingent on Intel improving yield before 2028.

Evolution: Consistent; more pessimistic on near-term Intel readiness than SemiAnalysis.

[7][13]

TSMC

CoWoS remains the dominant AI packaging technology, with revenue growing 30% YoY; CEO acknowledges supply will stay tight for years but presents ongoing demand as evidence of continued strength.

Evolution: Consistent; TSMC has not publicly responded to the Google-Intel packaging reports.

[10]

Google (via reported orders)

Reportedly committed to Intel EMIB-T at scale (3M+ units, 2028 target); no public confirmation from Google.

Evolution: No public statement; stance inferred from order reporting across multiple outlets.

[2][3][14][15]

MediaTek (via TrendForce reporting)

Reportedly adopting a dual Intel EMIB / TSMC CoWoS packaging strategy for AI ASIC designs, hedging between both technologies rather than committing exclusively to either.

Evolution: New voice this pass; first reported indication of a second major customer exploring EMIB for production AI packaging.

[11]

CommonWealth Magazine (Taiwan)

Questions whether Google's EMIB-T commitment is final and whether the order could revert to TSMC if Intel's yield targets are not met.

Evolution: Consistent skeptic on the permanence of the Google-Intel arrangement.

[8]

Trade press and market observers

TSMC's packaging concentration is a recognized systemic risk for AI supply chains; Intel EMIB-T is framed as the primary US-sourced structural alternative, with glass substrates as a longer-term option.

Evolution: WCCFTech this pass adds a supply chain sovereignty framing ('America's Answer') to what had been primarily a technical and commercial story.

[16][17][18][12]

Tensions

  • SemiAnalysis argues EMIB-T is technically compelling and commercially superior to CoWoS on scalability and cost; Ming-Chi Kuo argues Intel's current yield (~90%) is insufficient for volume production, making the transition a supply-chain gamble. [4][7]
  • SemiAnalysis's ECTC analysis shows Intel has validated EMIB-T at 2× reticle scale with expansion to 4.5× underway, but observed severe warpage at the 240 mm × 240 mm panel size relevant for large AI accelerators — progress and risk in the same disclosure. [5]
  • Multiple outlets report Google's 3M+ unit EMIB-T order as a firm commitment; CommonWealth Magazine questions whether the decision is final and could revert to TSMC if Intel yield targets are missed. [2][3][8]
  • Google's reported shift to Intel packaging is framed partly as supply diversification from TSMC; AMD and NVIDIA are simultaneously competing for the same TSMC CoWoS capacity, showing the broader market has not followed Google's direction. [4][9]
  • TSMC's growing CoWoS revenue and multi-year supply tightness confirm CoWoS as a durable bottleneck; Intel EMIB-T is the primary proposed alternative, but its manufacturing maturity at scale remains unproven. [10][6][5]

Sources

  1. [1] Google's next TPU, codenamed Humufish, is set to use Intel's EMIB-T instead of TSMC CoWoS. — SemiAnalysis Twitter (2026-07-01)
  2. [2] Intel Secures Google Order for Over 3 Million TPU Chips - Semicon electronics — reactive:google-tpu-emib-packaging
  3. [3] Google reportedly books Intel for packaging more than 3 million TPUs in 2028 — SK hynix is testing Intel's EMIB packaging for HBM integration | Tom's Hardware — reactive:google-tpu-emib-packaging
  4. [4] So why EMIB? — SemiAnalysis Twitter (2026-07-01)
  5. [5] EMIB-T Roadmap, Custom HBM, — SemiAnalysis Twitter (2026-07-02)
  6. [6] The risk. Plain EMIB has shipped in volume for years, but EMIB-T is new, and a power-delivering bridge is harder to manu… — SemiAnalysis Twitter (2026-07-01)
  7. [7] Google's TPU Supply Chain Gamble Intensifies: Intel's EMIB Yield Stuck at 90%, Kuo Points to TSMC's Dilemma — BigGo Finance — reactive:google-tpu-emib-packaging
  8. [8] Could Google's Next TPU Shift Back to TSMC? Inside the EMIB vs ... — reactive:google-tpu-emib-packaging
  9. [9] 🔴 AMD & NVIDIA: TAIWAN PACKAGING BIDDING WAR INTENSIFIES FOR 2027 CAPACITY — reactive:google-tpu-emib-packaging (2026-06-30)
  10. [10] TSMC's $TSM CoWoS Remains Central To AI Chip Boom. May Revenue +30% YoY. CEO Warns Supply Lag Will Last Years. — reactive:google-tpu-emib-packaging (2026-06-28)
  11. [11] [News] MediaTek Reportedly Adopts Dual Packaging Strategy With Intel EMIB, TSMC CoWoS for AI ASIC Push — reactive:google-tpu-emib-packaging
  12. [12] Intel's EMIB Challenges TSMC's CoWoS as America's Answer to the AI Packaging Bottleneck — reactive:google-tpu-emib-packaging
  13. [13] Ming-Chi Kuo on Intel's EMIB-T packaging for Google TPU v8e (Humufish) | SemiWiki — reactive:google-tpu-emib-packaging
  14. [14] Google Is Reportedly A Major Intel Foundry Customer, Will Use EMIB Advanced Packaging For Next-Gen TPU — reactive:google-tpu-emib-packaging
  15. [15] Google orders 3 million TPUs from Intel as TSMC strains - Quartz — reactive:great-ai-silicon-shortage
  16. [16] AI Chip Packaging Constraints Create an Opening for Intel’s EMIB Technology - 24/7 Wall St. — reactive:google-tpu-emib-packaging
  17. [17] A Niche Technology Became a Choke Point for A.I — reactive:google-tpu-emib-packaging (2026-06-26)
  18. [18] Nomura argues that most investors still focus on GPUs, CPUs, and foundries, while overlooking the deeper layers of the A... — reactive:google-tpu-emib-packaging (2026-07-01)
  19. [19] Intel's EMIB-T packaging technology set for fab rollout this year — as TSMC CoWoS capacity remains limited, EMIB-T is preparing for advanced AI accelerator designs | Tom's Hardware — reactive:google-tpu-emib-packaging
  20. [20] Intel's EMIB-T Packaging Pulls Two More Taiwanese Suppliers Into Google's TPU Orbit as TSMC's CoWoS Strains — reactive:google-tpu-emib-packaging
  21. [21] Glass Substrates Break AI Chip Packaging Bottleneck in 2026 — reactive:google-tpu-emib-packaging (2026-06-30)